A Better HF SDR Than RTL-SDR?
The idea is simple: build a low-cost HF receiver around a cheap high-speed ADC instead of repurposing an RTL-SDR. Teaser costs TARANG FPGA board (10K LUTs): < $15 ADC daughter board (with analog frontend filters and all): < $10 Total: < $25, or possibly much less Proposed architecture Hangzhou Ruimeng Tech MS9280 10-bit, 35 MSPS pipeline ADC Low-jitter 35 MHz sampling clock Switchable input filters, gain and attenuation Small FPGA for capture, digital down-conversion and decimation ...