The idea is simple: build a low-cost HF receiver around a cheap high-speed ADC instead of repurposing an RTL-SDR.
Teaser costs
TARANG FPGA board (10K LUTs): < $15
ADC daughter board (with analog frontend filters and all): < $10
Total: < $25, or possibly much less
Proposed architecture
Hangzhou Ruimeng Tech MS9280 10-bit, 35 MSPS pipeline ADC
Low-jitter 35 MHz sampling clock
Switchable input filters, gain and attenuation
Small FPGA for capture, digital down-conversion and decimation
Raspberry Pi Pico 2 (RP2350) for control and USB I/Q streaming
At 35 MSPS, the first Nyquist zone extends to 17.5 MHz, so the 20m band can be
received by direct sampling. The 10m band can be received using
undersampling: a 28 MHz signal aliases to about 7 MHz. A sharp 10m band-pass
filter is essential to prevent signals from other Nyquist zones from folding
into the same spectrum.
Why the MS9280?
The MS9280 datasheet is strikingly similar to the Analog Devices AD9280 datasheet: the supply range, package, reference and clamp features, OTR output, pipeline architecture and 135 MHz undersampling claim all line up. The MS9280 is therefore likely to be an enhanced AD9280 clone or derivative, extending the original 8-bit, 32 MSPS design to 10 bits and 35 MSPS.
The extra resolution is attractive, but it does not guarantee better reception by itself. Clock jitter, input filtering, front-end linearity and FPGA DSP will determine the real-world dynamic range.
The FPGA is probably not optional: the ADC produces 350 Mbit/s of raw sample data, far too much to stream directly over the RP2350's USB interface. The FPGA must reduce this to a narrow, manageable I/Q stream first.
Status
To be built and tested. The first measurements should cover usable ENOB, overload behaviour, clock sensitivity and 10m undersampling performance.
AD9280 reference datasheet
TARANG FPGA R1.0
