<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Direct Sampling on Dhiru's Notebook</title><link>https://rfcorner.in/tags/direct-sampling/</link><description>Recent content in Direct Sampling on Dhiru's Notebook</description><generator>Hugo</generator><language>en</language><lastBuildDate>Thu, 23 Jul 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://rfcorner.in/tags/direct-sampling/index.xml" rel="self" type="application/rss+xml"/><item><title>A Better HF SDR Than RTL-SDR?</title><link>https://rfcorner.in/posts/better-sdr-ideas-1/</link><pubDate>Thu, 23 Jul 2026 00:00:00 +0000</pubDate><guid>https://rfcorner.in/posts/better-sdr-ideas-1/</guid><description>&lt;p&gt;The idea is simple: build a low-cost HF receiver around a cheap high-speed ADC
instead of repurposing an RTL-SDR.&lt;/p&gt;
&lt;h2 id="teaser-costs"&gt;Teaser costs&lt;/h2&gt;
&lt;ul&gt;
&lt;li&gt;
&lt;p&gt;TARANG FPGA board (10K LUTs): &amp;lt; $15&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;ADC daughter board (with analog frontend filters and all): &amp;lt; $10&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Total: &amp;lt; $25, or possibly much less&lt;/p&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;h2 id="proposed-architecture"&gt;Proposed architecture&lt;/h2&gt;
&lt;ul&gt;
&lt;li&gt;
&lt;p&gt;Hangzhou Ruimeng Tech MS9280 10-bit, 35 MSPS pipeline ADC&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Low-jitter 35 MHz sampling clock&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Switchable input filters, gain and attenuation&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Small FPGA for capture, digital down-conversion and decimation&lt;/p&gt;</description></item></channel></rss>