Reversing the Huidu HD-R712 FPGA board
We are working on reversing the Huidu HD-R712 LED Display Full Color Receiving Card - a very cost-effective (~1000 INR) and widely available FPGA board. We draw inspiration from the https://github.com/q3k/chubby75 work. FPGA Blink Project Files 1 Random brain dump user@zion:~/repos/pico-dirtyJtag$ sudo openFPGALoader --cable dirtyJtag --freq 10000 --detect empty Jtag frequency : requested 10000Hz -> real 10000Hz index 0: idcode 0x4014c35 manufacturer anlogic family eagle d20 model EG4D20EG176 irlength 8 user@zion:~/repos/pico-dirtyJtag$ sudo openFPGALoader --cable dirtyJtag --detect empty Jtag frequency : requested 6000000Hz -> real 6000000Hz index 0: idcode 0x4014c35 manufacturer anlogic family eagle d20 model EG4D20EG176 irlength 8 JTAG pinout: V ┌───────────────────┐ │ 1 3 5 7 9 │ │ 2 4 6 8 10 │ └───────────────────┘ 9 => TCK 7 => TDO 5 => TMS 3 => NC (Not Connected) 1 => TDI user@zion:~/Dropbox/Huidu_FPGA$ make flash sudo openFPGALoader --cable dirtyJtag -v led.bit empty Jtag frequency : requested 6000000Hz -> real 6000000Hz found 1 devices index 0: idcode 0x4014c35 manufacturer anlogic family eagle d20 model EG4D20EG176 irlength 8 File type : bit Parse file header end DONE bitstream header infos Architecture: eagle_s20 Bitstream CRC: 1110011001000011 Date: 2026/ 2/27 8: 7 Design name: led Package: BG256 USER CODE: 00000000000000000000000000000000 Version: 5.0.28716 tool: Anlogic Infotech Corporation ASCII Bitstream Loading: [==================================================] 100.00% Done Basic IO constraints details set_pin_assignment {CLK_IN} { LOCATION = P62; } set_pin_assignment {led} { LOCATION = P81; } # This is the 'key+' header pin set_pin_assignment {uart_rx} { LOCATION = P42; } This is enough to get the LED and one-directional UART working! ...